Model

PG1006

Output

LVDS

connector

MDR 36Pin

Pixel Rate

1 Link up to 135MHz

2 Link up to 270MHz (135MHz x 2 )

4 Link up to 540MHz (135MHz x 4 )

Color Deep

R G B each channel 6/8/10 bits

VBL Output

Adjuster 0-26V@8~10A  Step0.01V

VDD Output

Adjuster 0-13V@4~5A   Step0.01V

Video Timing

Horizontal (clocks per line)

Total   up to 2048  Active  8-2040 2ch (4ch=2ch*2)

Vertical (lines per frame)

Total   up to 2048  Active   1-2047 2ch(4ch=2ch*2)

Test Pattern

Basic and has custom-made pattern

Software

Programmable timing and pattern by web server

Control signal

DOT-CLK  H sync  V sync  DE

Download Interface

LAN

Control Interface

RS232/ LAN

User Operate

Display LCD

Operate Key-stoke

Power Input

AC220V

Dimension

300mm*310mm*75mm

Operation Temperature

0~40°C

Storage Temperature

-20~60°C